Employing more stress testing at the wafer level improves quality while reducing burn-in time and cost. So why isn’t it ...

Next-generation optical inspection is about more than just sensitivity. It’s about reliably seeing through complexity.

Wafer-scale technology is making waves again, this time promising to enable artificial intelligence (AI) models with trillions of parameters to run faster and more efficiently than traditional ...

At Silicon Saxony Day 2025, Manuela Junghähnel, head of wafer-level system integration at Fraunhofer IZM-ASSID, laid out a roadmap that could redefine how Europe approaches advanced chip packaging on ...

Single-crystal indium phosphide (InP) wafers, characterized by atomic-scale surface roughness and minimal subsurface damage, are ideal substrates for high-frequency microwave devices, optoelectronic ...

Finally, the various improvements in wafer processing and wafer alignment during bonding will be discussed, resulting in high yield hybrid bonding down to 400nm interconnect pitch for wafer-to-wafer ...

Here, we report a polymer-free and dry-patterning technique for wafer-scale 2D semiconductors. Upon lamination of a three-dimensional Au stamp onto monolayer MoS 2 and then it being peeled away, the ...

As the temperature increases, the sample’s arching warpage further intensified, and when the maximum temperature was reached, the warpage value increased to a maximum of 56 μm. As the temperature ...