TSMC has announced that it's taped out its first 7nm EUV design, with 5nm risk production planned for Q2 2019. ... while the 5nm node will be capable of deploying EUV on up to 14 layers.

The TSMC N7+ node that can use EUV on up to four layers. Its N5 that will use EUV on up to 14 layers will be ready for risk production in April. EUV aims to lower costs by reducing the number of masks ...

The leading edge is currently at 7+ with about three layers done using EUV. In 2020, TSMC will ramp 5nm in the second half with significantly increased EUV usage of about 15 layers, followed by 6nm ...

Multiple masks per chip layer would simply add insult to injury. Instead, TSMC is banking on 0.33-NA EUV plus multi-patterning wizardry to keep its chips complex but not wallet-melting.

TSMC's new EUV process is hitting yield just in time for AMD's next-gen Zen 3 CPUs. Matching yields with the current 7nm process, N7+ will offer up to 20% greater density and 10% more performance ...

"TSMC is clearly leading the EUV pack, both in terms of tools taken and ordered, numbers of commercial EUV wafers produced and integration of EUV into their coming roadmap," says Jim Fontanelli, a ...

Meanwhile, some of ASML’s key customers have publicly reiterated their commitment to the new technology. Samsung says that it has now completed the development of its EUV process for manufacturing ...

Finally, though, in the last few years these EUV tools have reached commercialization, with TSMC 5nm the first node designed to make extensive use of EUV at multiple layers. This node is in volume ...

It is unclear how many of the machines TSMC has bought from ASML, but each High NA unit costs approximately $370 million a piece. Netherlands-based ASML is the sole global supplier of EUV ...

TSMC said that the EUV-enhanced node will offer another 10 percent of power savings while occupying around 15 percent less space. But Samsung is playing catchup with TSMC in terms of shipments.

TSMC has announced that it's taped out its first 7nm EUV design, with 5nm risk production planned for Q2 2019. Previous 7nm chips were and are built using conventional lithography.