Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU ...

A novel structure for a non-volatile flip-flop (NVFF) was proposed combining the in-series structure (MFMIM) of a ferroelectric capacitor and a dielectric capacitor followed by a CMOS-inverter. It was ...

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