TSMC will discuss its development of a monolithic CFET inverter on a 48nm gate pitch, equivalent to a 5nm process. The inverter features stacked n-type and p-type nanosheet transistors with ...

Imec highlights critical process steps and modules for monolithic CFET devices —The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) ...

Figure 2 The chip manufacturing technology could evolve from FinFET to CFET in nearly a decade. Source: imec. Next, imec anticipates that complementary FET (CFET) technology will further shrink the ...

After CFET transistors arrive, the next step of GAA is to change the materials used in NMOS and PMOS transistors to 2D ...

Fig. 5: Imec’s view of transistor roadmap. Imec proposes two options—CFETs and vertical nanowires. Slated for 2.5nm and beyond, a CFET is a more complex version of a gate-all-around device.

In the sequential approach, NMOS and PMOS transistors are processed on separate wafers, which are then bonded. “With the sequential CFET approach, the NMOS and PMOS devices can be formed on separate ...

Perspectives on future innovations in advanced transistors with new channel materials and ... and now to the cutting-edge vertical transistor 3D stacking in CFET/3DS-FET or vertical-channel ...

In particular, it is assumed that this node introduces the "CFET" transistor architecture that Intel disclosed in December 2021 with the comment that this could deliver a 30-50% shrink.