TSMC claims N2 defect density is lower than N3 defect density two quarters before mass production starts, reveals N2 HVM time frame.

TSMC is currently one of the most renowned companies in the tech industry. Its factories produce chips for major names in ...

TSMC claims its upcoming N2 manufacturing node is ahead of schedule on defect reduction, even though it is the company’s first attempt at gate-all-around (GAA) nanosheet transistor technology.

TSMC has the advantage of already being further ahead in developing its N2, 2nm-class node. It started taking orders in April, with Apple likely being its first major customer. But Intel recently ...

TSMC says that it remains on track to begin high-volume production of next-gen chips on its new N2 (2nm-class) process node, the first production tech that uses gate-all-around (GAA) nanosheet ...

TSMC held its North America Technology Symposium on Wednesday, April 23, 2025 at the Santa Clara Convention Center and ...

A14 uses TSMC’s 2nd Generation GAA (gate-all-around) nanosheet transistors—a key update from the first-gen GAA seen in the N2 series. Additionally, TSMC is introducing NanoFlex Pro ...

Next up on the docket are N2P and N3A, with the former being a power-optimized version of N2, and the latter being a modification of N3 for absolute maximum yield rates. Slide: TSMC A16 will come ...

Intel has reportedly placed orders with TSMC for its bleeding-edge 2nm-class N2 process technology ... rather than performance or yield concerns. To some extent, even Arrow Lake is dual-sourced ...

Next-generation AMD EPYC CPU, codenamed “Venice,” is the first HPC product to be brought up on TSMC’s next-generation N2 node ... power efficiency and yields for high-performance ...