Design-Reuse4y
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...
CU Boulder News & Events4y
ECEA 5361 Hardware Description Languages for FPGA Design
This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...
Design-Reuse17d
Avsbus slave ip verilog IP Listing
AVSBUS Slave interface provides full support for the two-wire/ three-wire AVSBUS Slave synchronous serial interface, compatible with version 1.3.1 Part III of PMBus Bus Specification. Through ... SPI ...