EDN

Timing Closure on FPGAs

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer ...
EDN

How to improve async interface testing on ATE

This paper discusses an approach to timing closure to eliminate non-determinism in an asynchronous interface while performing AC characterization on ATE (automatic test equipment). By closing the ...
Semiconductor Engineering

Avoiding Pitfalls While Specifying Timing Exceptions

Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where ...
Design-Reuse

Tiempo Unveils First Timing-Driven Design Flow for its Innovative Clockless Chip Design Technology

Grenoble, France – June 07, 2010 – Tiempo,SAS, a developer of innovative clockless technology for the design of low power integrated circuits (ICs), today announced its ability to support the use ...
Design-Reuse

A primer on processor-based emulation

FPGA-based emulation is more widely understood by engineers because engineers are used to designing with FPGAs. Much less well understood are processor-based emulators, and ample examples of ...